1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device having cell capacitors and a method of manufacturing the same.
2. Description of Related Art
Some recent model dynamic random access memories (DRAMs) use stacked capacitor type memory cells in which cell capacitors are formed above cell transistors. As compared to planar type memory cells, stacked capacitor type memory cells are characterized in that cell capacitors of high capacity can be formed in a small area.
Stacked capacitor type memory cells typically have cell capacitors of crown-shaped structure. A cell capacitor having such a structure includes a closed-bottomed cylindrical lower electrode, a capacitor insulation film that covers side and top surfaces of the lower electrode, and an upper electrode that covers the lower electrode via the capacitor insulation film. The lower electrode is connected to an underlying cell transistor by a capacitor contact plug which extends vertically.
Japanese Patent Application Laid-open No. 2004-31950 discloses a technique by which the lower electrodes of cell capacitors in stacked capacitor type memory cells can be formed in a fine line width. According to the technique, insulator sidewalls and conductor sidewalls are alternately formed to achieve the formation of lower electrodes in a fine line width.
There are several types of cell transistors. If planar cell transistors are applied to the stacked capacitor type memory cells, it is needed to devise the layout of bit lines etc. That is, planar cell transistors have two electrodes to be controlled, one connected with a capacitor contact plug and the other connected with a bit line contact plug. Since such electrodes to be controlled are arranged next to one another in the direction of bit lines, some contrivance is needed to avoid collision between capacitor contact plugs and bit lines. Specific measures that have been taken include: forming bit lines in a wavy wiring pattern; arranging cell transistors obliquely to bit lines; and forming bit lines in areas between cell transistors and arranging bit line contact plugs across boundaries between the bit lines and the cell transistors when seen in a plan view.
It is preferred, however, that bit lines be straight in shape, the longitudinal direction of cell transistors be parallel to the direction of bit lines, and bit lines be laid in positions overlapping cell transistors when seen in a plan view. A technology that allows such configuration is thus desired.